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Novas Enhances Assertion Debug Capability for SystemVerilog Users; Debug Leader Introduces Automation Features to Streamline Process for Understanding Assertion Failures in Complex Designs
SAN JOSE, Calif.—(BUSINESS WIRE)—July 10, 2006—
Novas Software, Inc., the leader in debug systems for
complex chip designs, today introduced a new set of capabilities that
streamline the process of analyzing and debugging assertion failures
for users of SystemVerilog Assertions (SVA). The new features use
Novas' patented behavior-based debug techniques to automate the
analysis of complex assertion behavior and enable quick isolation of
the root cause of failures. The enhancements are available in the
latest release of the Verdi(TM) Automated Debug System.
Design teams are adopting SVA to increase verification efficiency
and throughput. These techniques introduce new challenges from a debug
perspective. Debugging complex assertions has typically been a tedious
process, requiring manual interpretation of assertion results, careful
correlation of failure information with related design signals, and
time-consuming inspection of the assertion description itself to
isolate the actual cause of the failure.
Taking SVA Debug to the Next Level
With a new assertion evaluation engine and an integrated set of
viewing windows, the Verdi system automates the SVA debug process and
gives designers a more efficient way to understand the structural and
temporal relationships within the assertion constructs, as well as the
relationship between the assertions and the design itself. The Verdi
system directs the process of tracing from the assertion failure point
to the offending design signals, automatically decomposing the
assertion and identifying the parts of the description that contribute
to the failure.
The system performs analysis based on assertion results produced
by verification tools, but it can also derive the necessary
assertion-related details based solely on design signal data using its
built-in assertion evaluation engine. This evaluation engine enables a
flexible, interactive use model that supports assertion debug with
limited simulation data, as well as the ability to check modified
assertions without re-running simulation.
"As verification methodologies evolve to support new techniques,
engineers require expanded debug capabilities to realize the full
potential of these new methods. Assertions have been proven an
effective tool in the verification of complex designs, and they
introduce a new set of challenges that require specific debug
support," said George Bakewell, director of Product Marketing at
Novas. "With our Verdi system's new SVA capabilities, we provide a way
for designers to quickly and easily take full advantage of assertions
and the benefits they offer. These capabilities leverage assertions
and assertion results to further automate the debug process, utilizing
powerful new engines to augment and operate on the results produced by
other tools."
Integrated Viewing and Analysis
Engineers can import a design with SVA descriptions into the Verdi
environment, view and traverse the complete source code and hierarchy,
and easily inspect the structure of the assertions and their
connection to design signals. After loading assertion result
information (e.g., from simulation), users can analyze failure and
coverage information in a spreadsheet, sort and filter the data to
isolate the failures of interest, and view the results as waveforms or
annotated on top of the original SVA source code. The new assertion
analysis engine and window automatically decompose the assertion and
direct the tracing process from assertion failure point to
contributing sequences and expressions and ultimately to the
implicated design signals. Users can then trace to the root cause of
the problem in the design using the Verdi system's patented behavior
analysis technology.
Verdi's powerful assertion features can be used independent of
simulation through the built-in assertion evaluation engine. The
engine evaluates assertions based on the SVA descriptions and the
related signal data provided in Novas' Fast Signal Database (FSDB)
format - producing a new FSDB file containing the assertion. This
evaluation engine enables a flexible, interactive use model that
supports assertion debug with limited simulation data. Users can
modify, check, and re-check assertions without the need for repeated
simulation runs.
Availability
The assertion analysis feature is available with the third quarter
2006 release of the Verdi debug system. For more information about
Novas' automated debug products, visit
http://www.novas.com/Solutions/Verdi/.
About Novas
Novas Software, Inc. is the leading provider of design
comprehension solutions for engineers designing complex ICs, embedded
systems and SoCs. Novas' Verdi automated debug and Siloti(TM)
visibility enhancement products dramatically accelerate the process
for understanding and correcting design problems starting from
system-level specification through silicon implementation. Novas is
headquartered in San Jose, Calif. with offices in Europe, Japan and
Asia-Pacific. For more information, visit http://www.novas.com or
email info@novas.com.
Verdi and Siloti are trademarks of Novas Software, Inc. All other
trademarks or registered trademarks are the property of their
respective owners.
Note to editors: High-resolution graphics available.
Contact:
Novas Software, Inc., San Jose
Marketing Communications
Rob van Blommestein, 408-467-7872
Email Contact
or
Public Relations for Novas
Wired Island, Ltd.
Laurie Stanley, 925-224-8762
Email Contact
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